1. Field of the Invention
The present invention relates to gated clock circuits and, more particularly, to a gated clock circuit with a substantially increased control signal delay.
2. Description of the Related Art
A gated clock circuit is used to generate a gated clock signal that has aperiodic pulses which can be switched on and off, depending upon the logic state of a control signal that is synchronous with (has a fixed time delay with respect to) the rising edges of a periodic master clock signal. Being aperiodic, the pulses of the gated clock signal occur less frequently than the pulses of the periodic master clock signal.
A critical factor in power sensitive applications, such as battery driven appliances, is the power dissipation of the CMOS logic blocks which, in turn, depends upon the frequency of the clock signal. Since the gated clock pulses occur less frequently than the master clock pulses, CMOS logic blocks that are driven by the gated clock pulses can dissipate significantly less power. As a result, gated clock pulses are ideal for power sensitive applications.
FIGS. 1A–1B show timing diagrams that illustrate a pair of prior-art clock signals. As shown in FIGS. 1A–1B, a master clock signal MCLK has a number of periodic pulses PP that occur at regular intervals, while a gated clock signal GCLK has a number of aperiodic pulses AP that occur at irregular intervals. Thus, in this example, three gated clock pulses are generated during the same period that seven master clock pulses are generated, thereby providing a significant savings in power.
As further shown in FIGS. 1A–1B, the aperiodic pulses AP of the gated clock signal GCLK have pulse widths that are equal to the pulse widths of, and are in phase with, the periodic pulses PP of the master clock signal MCLK. As a result, the aperiodic pulses AP of the gated clock signal GCLK must not contain any glitches, i.e., clock pulses that are shorter in duration than the pulse widths of the master clock signal MCLK.
FIGS. 2A–2B show timing diagrams that illustrate a pair of prior-art clock signals. As shown in FIGS. 2A–2B, a master clock signal MCLK has a number of periodic pulses PP that occur at regular intervals, while a gated clock signal GCLK has a number of aperiodic pulses AP that occur at irregular intervals.
In addition, however, the gated clock signal GCLK also has a first short pulse P1, referred to as a glitch, where only the rising edge of the pulse is in phase with a master clock pulse. This glitch is highly undesirable because it represents an extra clock edge that can cause a system malfunction.
Further, the gated clock signal GCLK also has a second short pulse P2 where only the falling edge of the pulse is in phase with a master clock pulse. In most logic designs, gated clock signals with shortened pulses, such as shortened pulse P2, are highly undesirable because the shortened pulses can cause system timing errors and system logic errors.
FIG. 3 shows a block diagram that illustrates a prior-art, gated clock circuit 300. As shown in FIG. 3, gated clock circuit 300 is implemented with a logic AND gate that has a first input A connected to the master clock signal MCLK, a second input B connected to a control signal CG, and an output that outputs a gated clock signal GCLK.
FIGS. 4A–4C show timing diagrams that illustrate the operation of the master clock signal MCLK, the control signal CG, and the gated clock signal GCLK of gated clock circuit 300. As shown in FIGS. 4A–4C, when the control signal CG is asserted, the rising edge of the control signal CG follows a rising edge of the master clock signal MCLK by a delay D1. Thus, the first pulse of the gated clock signal GCLK has a pulse width PW1 that is shorter than the pulse width PW of a master clock pulse by the delay D1.
In addition, a second “glitch” pulse of the gated clock signal GCLK is formed that has a pulse width PW2 that is shorter than the pulse width PW of a master clock pulse. As shown, the falling edge of the control signal CG follows a rising edge of the master clock signal MCLK by a delay D2, which is equal to delay D1, thereby forming the glitch pulse.
As noted above, both types of timing delays can lead to significant timing and logic issues. One approach to providing a gated clock signal that has a pulse width that is equal to the pulse width of, and in phase with, a master clock pulse is to use a flip-flop and a logic gate to form a glitchless gated clock circuit.
FIG. 5 shows a block diagram that illustrates a prior art, glitchless gated clock circuit 500. As shown in FIG. 5, clock circuit 500 includes a falling-edge triggered flip-flop 510 that has a data input connected to receive a control signal CG, an inverted clock input connected to receive a master clock signal MCLK, and a Q output that generates a signal QOUT. With an inverted clock input, the logic state of the signal QOUT is the same as the logic state of the control signal CG after the falling edge of a master clock pulse.
As further shown in FIG. 5, clock circuit 500 includes a logic AND gate 512 that has a first input A connected to the signal QOUT, a second input B connected to the master clock signal MCLK, and an output that outputs a gated clock signal GCLK. Thus, flop 510 and AND gate 512 respond to different edges of the master clock signal MCLK.
FIGS. 6A–6D show timing diagrams that illustrate the operation of the master clock signal MCLK, the control signal CG, the signal QOUT, and the gated clock signal GCLK of gated clock circuit 500. As shown in FIGS. 6A–6D, when the control signal CG is asserted, the rising edge of the control signal CG follows a rising edge of a first master clock pulse by a delay D1. Similarly, the falling edge of the control signal CG follows the rising edge of a second master clock pulse by a delay D2, which may or may not be equal to delay D1.
On the falling edge of the first master clock pulse, flop 510 receives the logic high of the control signal CG and, after a clock-to-Q delay D3, drives the signal QOUT high. The signal QOUT then falls after delay D4, which may or may not be equal to delay D3, after the falling edge of the second master clock pulse.
As further shown in FIGS. 6A–6D, the rising and falling edges of the second master clock pulse then clock the logic state of the signal QOUT through AND gate 512 to form the gated clock signal GCLK with a phase and pulse width PW that match the phase and pulse width PW of the master clock signal MCLK.
Although gated clock circuit 500 generates full-width, glitch-free clock pulses, circuit 500 imposes a highly undesirable timing constraint on the control signal CG. As previously described, the rising edge of the control signal CG has a delay D1 with respect to a rising edge of the master clock signal MCLK.
However, as shown in FIGS. 6A–6D, flop 510 samples the control signal CG on the falling edge of the master clock signal MCLK. Therefore, the control signal CG only has one-half of the clock period (minus the set up time of flop 510) to become valid.
Stating this in equation form:D1MAX+TSETUP=PW,  EQ. 1where D1MAX is the maximum allowable delay for the rising edge of the control gate CG with respect to a rising edge of the master clock signal MCLK, TSETUP is the setup time of flop 510, and PW is the pulse width of the master clock signal MCLK.
Solving for D1MAX yields,D1MAX=PW−TSETUP,  EQ. 2
For most systems, the pulse width of the clock signal is equal to ½ of the clock period. In equation form, PW=TCLK/2, where TCLK represents a clock period.
Thus, EQ. 2 can be rewritten as:D1MAX=TCLK/2−TSETUP.  EQ. 3
The logic signals in a fully synchronous logic design usually have a full clock period (minus the flip-flop set up time) to become valid. However, as shown by EQ. 3, D1MAX is less than ½ of the clock period. As a result, the control signal CG must become valid in less than ½ of the clock period. In other words, the control signal CG must be twice as fast as the other logic signals. However, in many applications, especially in high speed logic applications, this condition is almost impossible to meet.